Semiconductor device including cell region and peripheral region having high breakdown voltage structure

ABSTRACT

A semiconductor device includes a semiconductor substrate and an electric field terminal part. The semiconductor substrate includes a substrate, a drift layer disposed on a surface of the substrate, and a base layer disposed on a surface of the drift layer. The semiconductor substrate is divided into a cell region in which a semiconductor element is disposed and a peripheral region that surrounds the cell region. The base region has a bottom face located on a same plane throughout the cell region and the peripheral region and provides an electric field relaxing layer located in the peripheral region. The electric field terminal part surrounds the cell region and a portion of the electric field relaxing layer and penetrates the electric field relaxing layer from a surface of the electric field relaxing layer to the drift layer.

CROSS REFERENCE TO RELATED APPLICATIONS

The present application is based on and claims priority to JapanesePatent Application No. 2010-141744 filed on Jun. 22, 2010, the contentsof which are incorporated in their entirety herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device that includes acell region in which a semiconductor element is disposed and aperipheral region surrounding the cell region and having a highbreakdown voltage structure.

2. Description of the Related Art

JP-A-11-74524 (corresponding to U.S. Pat. No. 6,054,752) andJP-A-2007-165604 (corresponding to U.S. Pat. No. 2009/0045413 A1)disclose high breakdown voltage structures formed in a peripheral regionsurrounding a cell region in which a semiconductor element such as avertical power MOSFET and a diode is formed. FIG. 13 is across-sectional view of a high breakdown voltage structure formed in aperipheral region of a semiconductor device disclosed in JP-A-11-74524.

As shown in FIG. 13, the semiconductor device includes an n type driftlayer 101, a p type layer 102 disposed on the n type drift layer 101, arecess section 103, and an electric field relaxing layer 104 having a ptype. The recess section 103 forms a mesa structure and the electricfield relaxing layer 104 is disposed on a sidewall and a bottom of themesa structure. The recess section 103 for forming the mesa structure isprovided from the p type layer 102 into the n type drift layer 101. At astepped portion of the mesa structure, the electric field relaxing layer104 is disposed from a surface of the p type layer 102 to a surface ofthe n type drift layer 101 in the recess section 103. By forming theelectric field relaxing layer 104, equipotential lines gently extendtoward a peripheral region, and an electric field concentration isrelaxed. Thus, a breakdown voltage can be improved.

The high breakdown voltage structures disclosed in JP-A-11-74524 andJP-A-2007-165604 have a discontinuous point where materials havingdifferent conductivity types are connect with each other at a portionbeing in contact with the electric field relaxing layer and a bendingportion at which an electric field relaxing layer is bent. For example,in the high breakdown voltage structure disclosed in JP-A-11-74524, adiscontinuous point where an n type semiconductor connects with a p typesemiconductor is located at a region R1 in FIG. 13, and a bendingportion of the electric field relaxing layer is located at a region R2in FIG. 13. Thus, the electric field may concentrate at the regions R1and R2, and the breakdown voltage may be reduced.

SUMMARY OF THE INVENTION

In view of the foregoing problems, it is an object of the presentinvention to provide a semiconductor device that includes a peripheralregion having a high breakdown voltage structure.

A semiconductor device according to an aspect of the present inventionincludes a semiconductor substrate and an electric field terminal part.The semiconductor substrate includes a substrate, a drift layer of afirst conductivity type disposed on a surface of the substrate, and abase layer of a second conductivity type disposed on a surface of thedrift layer. The semiconductor substrate is divided into a cell regionin which a semiconductor element is disposed and a peripheral regionthat surrounds the cell region. The base region has a bottom facelocated on a same plane throughout the cell region and the peripheralregion. A portion of the base region located in the peripheral regionprovides an electric field relaxing layer. The electric field terminalpart is disposed in the peripheral region and surrounds the cell regionand a portion of the electric field relaxing layer. The electric fieldterminal part penetrates the electric field relaxing layer from asurface of the electric field relaxing layer to the drift layer.

In the above-described semiconductor device, the electric field relaxinglayer is provided by a portion of the base layer having a flat bottomface. Thus, the electric field relaxing layer does not have a bendingportion. In addition, because the drift layer is only semiconductorbeing in contact with the electric field relaxing layer, there is nodiscontinuous point where materials having different conductivity typesare connected with each other. Accordingly, a breakdown voltage of thesemiconductor device can be improved.

BRIEF DESCRIPTION OF THE DRAWINGS

Additional objects and advantages of the present invention will be morereadily apparent from the following detailed description of preferredembodiments when taken together with the accompanying drawings. In thedrawings:

FIG. 1 is a cross-sectional view of a SiC semiconductor device accordingto a first embodiment;

FIG. 2A is a cross-sectional view of a SiC semiconductor deviceaccording to the first embodiment used as a simulation model, and FIG.2B is a diagram showing a distribution of equipotential lines at abreakdown of the model shown in FIG. 2A;

FIG. 3 is a graph showing a relationship between a drain voltage and adrain current at reverse bias;

FIG. 4 is a graph showing a relationship between an impurityconcentration of a p type base layer and an electric field relaxinglayer and a breakdown voltage;

FIG. 5 is a graph showing a relationship between a thickness of anelectric field relaxing layer and a breakdown voltage;

FIG. 6A and FIG. 6B are diagrams showing processes of manufacturing theSiC semiconductor device shown in FIG. 1;

FIG. 7A and FIG. 7B are diagrams showing process of manufacturing theSiC semiconductor device following the process shown in FIG. 6B;

FIG. 8A and FIG. 8B are diagrams showing processes of manufacturing theSiC semiconductor device following the process shown in FIG. 7B;

FIG. 9 is a cross-sectional view of a SiC semiconductor device accordingto a second embodiment;

FIG. 10 is a cross-sectional view of a SiC semiconductor deviceaccording to a third embodiment;

FIG. 11 is a cross-sectional view of a SiC semiconductor deviceaccording to a fourth embodiment;

FIG. 12 is a cross-sectional view of a SiC semiconductor deviceaccording to a fifth embodiment; and

FIG. 13 is a cross-sectional view of a SiC semiconductor deviceaccording to a prior art.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment

A first embodiment of the present invention will be described. In thepresent embodiment, a SiC semiconductor device in which an n channeltype vertical power MOSFET is formed in a cell region as a semiconductorelement will be described. FIG. 1 is a cross-sectional view of the SiCsemiconductor device according to the present embodiment. Aconfiguration of the SiC semiconductor device according to the presentembodiment will be described below with reference to FIG. 1.

As shown in FIG. 1, the SiC semiconductor device includes the cellregion in which the vertical power MOSFET is formed and a peripheralregion surrounding the cell region and having a high breakdown voltagestructure. Although only a part of the cell region and the peripheralregion in the SiC semiconductor device is shown in FIG. 1, the cellregion is located at a center portion of the SiC semiconductor deviceand the peripheral region surrounds the cell region.

The SiC semiconductor device includes a semiconductor substrate 4. Thesemiconductor substrate 4 includes an n+ type substrate 1, an n− typedrift layer 2, and a p type base layer 3. The n+ type substrate 1 has animpurity concentration of, for example, greater than or equal to 1×10¹⁹cm⁻³. The n− type drift layer 2 has a lower impurity concentration thanthe n+ type substrate 1. For example, the n− type drift layer 2 has animpurity concentration of from 1×10¹⁵ cm⁻³ to 5×10¹⁶ cm⁻³. The p typebase layer 3 has an impurity concentration of, for example, from 1×10¹⁶cm⁻³ to 5×10¹⁸ cm⁻³. All of the n+ type substrate 1, the n− type driftlayer 2, and the p type base layer 3 are made of SiC, which is wide gapsemiconductor.

The semiconductor substrate 4 is divided into the cell region and theperipheral region. In the cell region, an n+ type source region 5 havinga higher impurity concentration than the n− type drift layer 2 isdisposed. For example, the n+ type source region 5 has an impurityconcentration of from 1×10¹⁸ cm⁻³ to 5×10²° cm⁻³. In addition, on afront-surface side of the semiconductor substrate 4, a trench 6penetrates the n+ type source region 5 and the p type base layer 3 tothe n− type drift layer 2. A gate insulating layer 7 is disposed so asto cover an inner wall of the trench 6. On a surface of the gateinsulating layer 7, a gate electrode 8 made of doped polysilicon isdisposed. An interlayer insulating layer 9 made of, for example, anoxide layer, is disposed so as to cover the gate electrode 8, and asource electrode 10 is disposed on the interlayer insulating layer 9.The source electrode 10 is electrically coupled with the n+ type sourceregion 5 and the p type base layer 3 through a contact hole 9 a providedin the interlayer insulating layer 9.

On a rear-surface side of the semiconductor substrate 4 including thecell region, that is, on an opposite side of the n+ type substrate 1from the n− type drift layer 2, a drain electrode 11 is disposed. Thevertical power MOSFET has the above-described configuration. Althoughonly one cell of the vertical power MOSFET is shown in FIG. 1, aplurality of cells of the vertical power MOSFET shown in FIG. 1 isdisposed in the cell region. The gate electrode 8 is electricallycoupled with an external device through a contact hole provided in theinterlayer insulating layer 9 on a cross section different from thecross section shown in FIG. 1.

In the semiconductor substrate 4, the p type base layer 3 extends fromthe cell region into the peripheral region. The p type base layer 3 hasa flat bottom face located on the same plane throughout the cell regionand the peripheral region. In the present embodiment, a portion of the ptype base layer 3 located in the peripheral region provides an electricfield relaxing layer 3 a.

In the peripheral region, a recess section 12 is formed by removing aportion of the p type base layer 3 from the surface of the p type baselayer 3 so as to form a mesa structure. The recess section 12 forforming the mesa structure is shallower than the p type base layer 3. Athickness of the p type base layer 3 that remain under the recesssection 12 is determined in accordance with the impurity concentrationof the p type base layer 3. For example, when the p type base layer 3has an impurity concentration of 1×10¹⁷ cm⁻³, the thickness of the ptype base layer 3 that remains under the recess section 12 is greaterthan or equal to 0.4 μm.

The cell region and a portion of the electric field relaxing layer 3 aare surrounded by an electric field terminal part 13. The electric fieldterminal part 13 is located on the bottom face of the recess section 12for forming the mesa structure. Specifically, the electric fieldterminal part 13 is disposed at a distance of from 1 μm to 1000 μm froma stepped portion of the recess section 12 adjacent to the cell region.The electric field terminal part 13 penetrates the electric fieldrelaxing layer 3 a from the surface of the electric field relaxing layer3 a to the n− type drift layer 2, and thereby the electric fieldrelaxing layer 3 a is divided.

In the present embodiment, the electric field terminal part 13 includesa plurality of grooves 14 penetrating the electric field relaxing layer3 a from the surface of the electric field relaxing layer 3 a to the n−type drift layer 2 and an insulating member 15 disposed in the grooves14. The gate insulating layer 7 and the interlayer insulating layer 9formed in the cell region extends to the peripheral region, and a partof the gate insulating layer 7 and the interlayer insulating layer 9provides the insulating member 15. The grooves 14 concentricallysurround the cell region and a portion of the electric field relaxinglayer 3 a. In other words, the electric field terminal part 13 accordingto the present embodiment includes a plurality of portions located atequal intervals, and each portion has a frame shape concentricallysurrounding the cell region.

The distance from the stepped portion of the recess section 12 to theelectric field terminal part 13 may be determined optionally. However, amisalignment of a mask may affect the cell region when the distance isless than 1 μm, and a chip size is large when the distance is greaterthan 10000 μm. Thus, it is preferable that the distance from the steppedportion of the recess section 12 to the electric field terminal part 13is from 1 μm to 10000 μm.

In this way, in the SiC semiconductor device according to the presentembodiment, the electric field relaxing layer 3 a for forming a highbreakdown voltage structure is provided by the portion the p type baselayer 3 located in the peripheral region. Thus, the electric fieldrelaxing layer 3 a does not have a bending portion. Furthermore, becausethe n− type drift layer 2 is only semiconductor being in contact withthe electric field relaxing layer 3, there is no discontinuous pointwhere materials having different conductivity types are connected witheach other. Accordingly, the breakdown voltage of the SiC semiconductordevice can be further improved.

FIG. 2A, FIG. 2B, and FIG. 3 are diagrams showing simulation results ofthe breakdown voltage of a SiC semiconductor device according to thepresent embodiment.

FIG. 2A is a cross-sectional view of a SiC semiconductor deviceaccording to the present embodiment used as a simulation model. FIG. 2Bis a diagram showing a distribution of equipotential lines at abreakdown of the model shown in FIG. 2A. In the simulation, the n− typedrift layer 2 has an impurity concentration of 5×10¹⁵ cm⁻³, and the ptype base layer 3 and the electric field relaxing layer 3 a have animpurity concentration of 1×10¹⁷ cm⁻³. In FIG. 2B, the equipotentiallines are shown at intervals of 70 V.

As shown in FIG. 2, the equipotential lines at the breakdown expandwidely without bias and terminate at the electric field terminal part13. A PN junction by the electric field relaxing layer 3 a and the n−type drift layer 2 forms a depletion layer, and the equipotential linesare expanded toward the peripheral region by the depletion layer. Thus,the equipotential lines expand widely in the peripheral region withoutbias. This means that electric field is generated without bias andelectric field concentration does not occur. If distortion occurs at aportion of the equipotential lines, electric field concentration occursat the portion. However, in the simulation result shown in FIG. 2B,there is no distortion. Thus, it can be considered that electric fieldconcentration does not occur. Also from the simulation result, it can beconfirmed that the breakdown voltage is further improved.

FIG. 3 is a graph showing a relationship between a drain voltage and adrain current at reverse bias. As shown in FIG. 3, the drain current isnot generated in cases where a drain voltage is less than 1900 V. Thus,the SiC semiconductor device is not broken down until the drain voltagereaches 1900 V.

FIG. 4 is a graph showing a relationship between the impurityconcentration of the p type base layer 3 and the electric field relaxinglayer 3 a and a breakdown voltage of the model shown in FIG. 2A. Asshown in FIG. 4, the breakdown voltage changes with the impurityconcentration of the p type base layer 3 and the electric field relaxinglayer 3 a. The SiC semiconductor device is designed so as to have abreakdown voltage of, for example, greater than or equal to 1200 V. Whenthe impurity concentration of the electric field relaxing layer 3 a isgreater than or equal to 1×10¹⁶ cm⁻³, the breakdown voltage can begreater than or equal to 1200 V.

However, when the impurity concentration of the electric field relaxinglayer 3 a is too high, the breakdown voltage is reduced. As describedabove, the equipotential lines expand as shown in FIG. 2B because thedepletion layer is formed by the PN junction by the electric fieldrelaxing layer 3 a and the n− type drift layer 2. When the impurityconcentration of the electric field relaxing layer 3 a is too high, awidth of the depletion layer expanding in the electric field relaxinglayer 3 a is reduced, and the breakdown voltage is reduced. An upperlimit of the impurity concentration of the electric field relaxing layer3 a is 2.5×10¹⁷ cm⁻³. Thus, when the impurity concentration of theelectric field relaxing layer 3 a is from 1×10¹⁶ cm⁻³ to 2.5×10¹⁷ cm⁻³,a breakdown voltage of greater than or equal to 1200 V can be achieved.

FIG. 5 is a graph showing a relationship between a thickness of theelectric field relaxing layer 3 a and the breakdown voltage. In thissimulation, the impurity concentration of the p type base layer 3 andthe electric field relaxing layer 3 a is 1×10¹⁷ cm⁻³.

As shown in FIG. 4, the breakdown voltage basically depends on theimpurity concentration of the electric field relaxing layer 3 a.However, when the thickness of the electric field relaxing layer 3 a istoo small, a predetermined breakdown voltage may not be achieved. Thisis because the breakdown voltage also depends on the whole amount ofimpurities included in the electric field relaxing layer 3 a. Thus, asshown in FIG. 5, the breakdown voltage is reduced with decrease in thethickness of the electric field relaxing layer 3 a. For example, in acase where the impurity concentration of the p type base layer 3 and theelectric field relaxing layer 3 a is 1×10¹⁷ cm⁻³, when the thickness ofthe electric field relaxing layer 3 a is 0.4 μm, the breakdown voltageis 1200 V. Thus, for example, in the case where the impurityconcentration of the p type base layer 3 and the electric field relaxinglayer is 1×10¹⁷ cm⁻³, a desired voltage can be achieved by setting thethickness of the electric field relaxing layer 3 a to be greater than orequal to 0.4 μm.

In the above description, the impurity concentration and the thicknessof the electric field relaxing layer 3 a are determined so as to achievea breakdown voltage of greater than or equal to 1200 V. However, adesired breakdown voltage may vary, and the impurity concentration andthe thickness of the electric field relaxing layer 3 a may be changed inaccordance with the desired breakdown voltage.

Next, a manufacturing method of the SiC semiconductor device accordingto the present embodiment will be described with reference to FIG. 6A toFIG. 8B.

In a process shown in FIG. 6A, the semiconductor substrate 4 in whichthe n− type drift layer 2 and the p type base layer 3 are stacked abovethe front surface of the n+ type substrate 1 in order is prepared. Then+ type substrate 1 has an impurity concentration of, for example,greater than or equal to 1×10¹⁹ cm⁻³, the n− type drift layer 2 has animpurity concentration of, for example, from 1×10¹⁵ cm⁻³ to 5×10¹⁸ cm⁻³,and the p type base layer 3 has an impurity concentration of, forexample, from 1×10¹⁶ cm⁻³ to 5×10¹⁸ cm⁻³. The n− type drift layer 2 andthe p type base layer 3 can be formed above the front surface of the n+type substrate 1 by epitaxial growth. On the rear surface of thesemiconductor substrate 4, the drain electrode 11 is formed.

In a process shown in FIG. 6B, a mask made of, for example, lowtemperature oxide (LTO) is formed on the surface of the p type baselayer 3. The mask is opened at a portion where the recess portion 12 isto be formed by a photolithography process. Then, the semiconductorsubstrate 4 is treated with etching such as reactive ion etching (RIE)with the mask, and the recess portion 12 is formed. Then, the mask isremoved.

In a process shown in FIG. 7A, a mask made of LTO is formed on thesurface of the p type base layer 3, and the mask is opened at a portionwhere the electric field terminal part 13 is to be formed by aphotolithography process. Then, the semiconductor substrate 4 is treatedwith etching such as RIE with the mask, and the grooves 14 are providedin the recess portion 12. Then, the mask is removed.

In a process shown in FIG. 7B, a mask having an opening at a portionwhere the n+ type source region 5 is to be formed is disposed, and anion implantation process of n type impurities such as nitrogen and anactivation process of the n type impurities are performed. Accordingly,the n+ type source region 5 is formed at a predetermined region in thesurface portion of the p type base layer 3 in the cell region. After themask is removed, a mask having an opening at a portion where the trench6 is to be formed is disposed, and etching is performed with the mask.Accordingly, the trench 6 is formed. After that, the mask is removed,and the gate insulating layer 7 is formed by gate oxidation. At thisprocess, the insulating layer is formed not only in the cell region butalso in the peripheral region, and thereby a part of the insulatingmember 15 is formed in the grooves 14.

In a process shown in FIG. 8A, a doped polysilicon layer is formed inthe whole area of the cell region and the peripheral region. The dopedpolysilicon layer is treated with etching or patterning with a mask, andthereby the gate electrode 8 is formed. Then, the interlayer insulatinglayer 9 made of, for example, LTO is formed in the whole are of the cellregion and the peripheral region by deposition. Accordingly, the grooves14 are fully filled with the insulating member 15, and the electricfield terminal part 13 is formed.

In a process shown in FIG. 8B, a mask having an opening at a portionwhere the contact hole 9 a and other holes are to be formed is disposedon the surface of the interlayer insulating layer 9. The interlayerinsulating layer 9 is treated with patterning with the mask, and therebythe contact hole 9 a and the other holes are provided.

After that, the source electrode 10 is formed on the surface of theinterlayer insulating layer 9. Accordingly, the source electrode 10 isdisposed also in the contact hole 9 a, and the source electrode 10 iselectrically coupled with the n+ type source region 5 and the p typebase layer 3. By the above-described way, the SiC semiconductor deviceaccording to the present embodiment can be formed.

As described above, in the SiC semiconductor device according to thepresent embodiment, the electric field relaxing layer 3 a for formingthe high breakdown voltage structure in the peripheral region isprovided by the portion of the p type base layer 3 having the flatbottom face. Thus, the electric field relaxing layer 3 a does not have abending portion. Furthermore, because the n− type drift layer 2 is onlya semiconductor being in contact with the electric field relaxing layer3 a, there is no discontinuous point where material having differentconductivity types are connected with each other. Therefore, thebreakdown voltage of the SiC semiconductor device can be furtherimproved.

Second Embodiment

A SiC semiconductor device according to a second embodiment will bedescribed. In the present embodiment, a configuration of an electricfield terminal part 13 is changed from the first embodiment, and otherparts of the SiC semiconductor device are similar to those of the firstembodiment. Thus, only a part different the first embodiment will bedescribed.

FIG. 9 is a cross-sectional view of the SiC semiconductor deviceaccording to the present embodiment. As shown in FIG. 9, the electricfield terminal part 13 includes only one groove 14 filled with theinsulating member 15, and the groove 14 has a frame shape. In this way,the electric field terminal part 13 does not need to have a plurality ofgrooves 14 filled with the insulating member 15 and may also have onegroove 14 filled with the insulating member 15.

A manufacturing method of the SiC semiconductor device according to thepresent embodiment is almost similar to the manufacturing method of theSiC semiconductor device according to the first embodiment. However, inthe process of forming the groove 14 shown in FIG. 7A, a mask pattern ischanged so that only one groove 14 is formed.

Third Embodiment

A SiC semiconductor device according to a third embodiment will bedescribed with reference to FIG. 10. In the present embodiment, aconfiguration of an electric field terminal part 13 is changed from thefirst embodiment, and other parts of the SiC semiconductor device aresimilar to those of the first embodiment. Thus, only a part differentthe first embodiment will be described.

FIG. 10 is a cross-sectional view of the SiC semiconductor deviceaccording to the present embodiment. As shown in FIG. 10, in the presentembodiment, an electric field terminal part 13 includes an n+ type layer16. The n+ type layer 16 can be formed, for example, by implanting ntype impurities after forming the recess section 12 and activating the ntype impurities by a heat treatment.

In this way, the electric field terminal part 13 may also be formed ofthe n+ type layer 16 having a different conductivity type from theelectric field relaxing layer 3 a.

A manufacturing method of the SiC semiconductor device according to thepresent embodiment is almost similar to the manufacturing method of theSiC semiconductor device according to the first embodiment. However, aprocess of forming the n+ type layer 16 is performed instead of theprocess of forming the grooves 14. The n+ type layer 16 can be formed,for example, by disposing a mask having an opening at a portion wherethe n+ type layer 16 is to be formed, implanting n type impuritiesthrough the mask, and activating the n type impurities by a heattreatment. When the n+ type layer 16 and the n+ type source region 5 areformed at the same process, the manufacturing process can be simplified.

Fourth Embodiment

A SiC semiconductor device according to a fourth embodiment will bedescribed. In the present embodiment, a configuration of an electricfield terminal part 13 is changed from the first embodiment, and otherparts of the SiC semiconductor device are similar to those of the firstembodiment. Thus, only a part different the first embodiment will bedescribed.

FIG. 11 is a cross-sectional view of the SiC semiconductor deviceaccording to the present embodiment. As shown in FIG. 11, in the presentembodiment, a recess section 12 for forming a mesa structure is notprovided in the whole area of a peripheral region but is provided at theinside of an outermost portion of the peripheral region, and an electricfield terminal part 13 is disposed outside the recess section 12.

In this way, the electric field terminal part 13 may also be disposedoutside the recess section 12 for forming the mesa structure.

A manufacturing method of the SiC semiconductor device according to thepresent embodiment is almost similar to the manufacturing method of theSiC semiconductor device according to the first embodiment. However, aprocess of forming a groove 14 is different from the first embodiment.In the first embodiment, the grooves 14 are formed at the process nextto the process of forming the recess section 12. However, in the presentembodiment, the process of forming the groove 14 is performed at thesame time as the process of forming the trench 6. While the gateinsulating layer 7 is formed and while the interlayer insulating layer 9is formed, the insulating member 15 is formed in the groove 14. When thedoped polysilicon layer for forming the gate electrode 8 is formed, thedoped polysilicon layer is disposed also in the groove 14. However, whenthe doped polysilicon layer is treated with patterning, the dopedpolysilicon layer in the groove 14 is removed.

Fifth Embodiment

A SiC semiconductor device according to a fifth embodiment will bedescribed. In the present embodiment, a configuration of an electricfield terminal part 13 is changed from the fourth embodiment, and otherparts of the SiC semiconductor device are similar to those of the fourthembodiment. Thus, only a part different the fourth embodiment will bedescribed.

FIG. 12 is a cross-sectional view of the SiC semiconductor deviceaccording to the present embodiment. In the present embodiment, a groove14 is provided outside the recess section 12 for forming the mesastructure, and the groove 14 is filled with the gate insulating layer 7and a polysilicon layer 17 in a manner similar to the trench gate in thecell region.

In this way, the electric field terminal part 13 may be disposed outsidethe recess section 12 for forming the mesa structure and the electricfield terminal part 13 may have the same structure as the trench gateformed in the cell region.

A manufacturing method of the SiC semiconductor device according to thepresent embodiment is almost similar to the manufacturing method of theSiC semiconductor device according to the fourth embodiment. In thefourth embodiment, the doped polysilicon layer that is formed in thegroove 14 when the gate electrode 8 is formed is removed. However, inthe present embodiment, the doped polysilicon layer in the groove 14 isnot removed and remains as the polysilicon layer 17.

Other Embodiments

Although the present invention has been fully described in connectionwith the preferred embodiments thereof with reference to theaccompanying drawings, it is to be noted that various changes andmodifications will become apparent to those skilled in the art.

Each semiconductor device according to the above-described embodimentsincludes the vertical power MOSFET as an example of a semiconductorelement disposed in the cell region. Each semiconductor device mayinclude a semiconductor element having other structure as long as thesemiconductor element includes the p type base layer 3. For example,each semiconductor devices may also include an IGBT in which theconductivity type of the n+ type substrate 1 is inverted to a p type ora PN diode in which the p type base layer 3 functions as an anode andthe n− type drift layer 2 and the n+ type substrate 1 function ascathodes.

Each semiconductor device according to the above-described embodimentsincludes the recess section 12 for forming the mesa structure. Therecess section 12 for forming the mesa structure may be omitted fromeach semiconductor device.

In each semiconductor device according to the above-describedembodiments, a first conductivity type is the n type, and a secondconductivity type is the p type as an example. The conductivity type ofeach component may be inversed.

Each semiconductor device according to the above-described embodimentsis made of SiC which is a wide band gap semiconductor. Eachsemiconductor device may also be made of GaN or diamond, which are widebad gap semiconductor having potential of achieving a high breakdownvoltage.

What is claimed is:
 1. A semiconductor device comprising: asemiconductor substrate including a substrate, a drift layer of a firstconductivity type disposed on a surface of the substrate, and a baselayer of a second conductivity type disposed on a surface of the driftlayer; and an electric field terminal part, wherein the semiconductorsubstrate is divided into a cell region in which a semiconductor elementis disposed and a peripheral region that surrounds the cell region, thebase region has a bottom face located on a same plane throughout thecell region and the peripheral region, a portion of the base regionlocated in the peripheral region provides an electric field relaxinglayer, the electric field terminal part is disposed in the peripheralregion, the electric field terminal part surrounds the cell region and aportion of the electric field relaxing layer, and the electric fieldterminal part penetrates the electric field relaxing layer from asurface of the electric field relaxing layer to the drift layer, whereinthe electric field relaxing layer reaches a channel forming part of thecell region.
 2. The semiconductor device according to claim 1, whereinthe electric field terminal part includes at least one groovepenetrating the electric field relaxing layer from the surface of theelectric field relaxing layer to the drift layer and an insulatingmember disposed in the at least one groove.
 3. The semiconductor deviceaccording to claim 2, wherein the at least one groove includes aplurality of grooves, the insulating member is disposed in each of theplurality of grooves, and the plurality of grooves concentricallysurrounds the cell region and the portion of the electric field relaxinglayer.
 4. The semiconductor device according to claim 1, wherein theelectric field terminal part includes a first conductivity type layerthat penetrates the electric field relaxing layer from the surface ofthe electric field relaxing layer to the drift layer.
 5. Thesemiconductor device according to claim 1, wherein the semiconductorsubstrate has a recess section in the peripheral region, the recesssection is formed by removing a portion of the base layer from a surfaceof the base layer so as to form a mesa structure, and the electric fieldterminal part is disposed in the recess section.
 6. The semiconductordevice according to claim 1, wherein the semiconductor substrate has arecess section in the peripheral region, the recess section is formed byremoving a portion of the base layer from a surface of the base layer soas to form a mesa structure, and the electric field terminal part isdisposed outside the recess section.
 7. The semiconductor deviceaccording to claim 5, wherein the recess section has a stepped portionadjacent to the cell region, and the electric field terminal part islocated at a distance of from 1 μm to 1000 μm from the stepped portion.8. The semiconductor device according to claim 1, wherein the base layerand the electric field relaxing layer have an impurity concentration offrom 1×10¹⁶ cm⁻³ to 2.5×10¹⁷ cm⁻³.
 9. The semiconductor device accordingto claim 1, wherein: the semiconductor element in the cell region is aNPN transistor.
 10. The semiconductor device according to claim 9,wherein: the NPN transistor includes a gate electrode in a trench via aninsulating layer, a source region attached to the trench and disposed ina surface portion of the base layer, and a drain electrode disposed on asubstrate, the trench penetrates the base layer and reaches the driftlayer, the channel forming part of the cell region is disposed betweenthe source region and the drift layer in the base layer, and attached toa sidewall of the trench.
 11. The semiconductor device according toclaim 1, wherein: the base layer includes a plurality of thicknesses.12. The semiconductor device according to claim 11, wherein: theplurality of thicknesses includes a first thickness of a first part ofthe base layer and a second thickness of a second part of the baselayer; the first part is nearer the cell region than the second part;and the first thickness is larger than the second thickness.
 13. Thesemiconductor device according to claim 1, wherein: the electric fieldrelaxing layer reaches the channel forming part of the cell regionthrough the portion of the base layer located in the peripheral regionthat provides the electric field relaxing layer.
 14. The semiconductordevice according to claim 1, wherein: the electric field relaxing layerdoes not have a bending portion.
 15. The semiconductor device accordingto claim 1, wherein: of all device semiconductor layers, only the driftlayer is in contact with the electric field relaxing layer.